Semiconductor devices such as ball grid array (BGA) packaged ICs are inevitably subject to a testing process prior to their final completion or incorporation into electronic apparatus. The testing process includes but is not limited to, testing of singulated devices either bare die, packaged IC (temporary or permanent), or variants in between. Commonly, electrical testing is accomplished by means of automatic test equipment (ATE) configured for stimulating semiconductor devices and then examining their output for proper functioning. In general, contact pins associated with the ATE are placed in physical and electrical contact with metallized contact surfaces of a device under test (DUT). These surfaces may include test pads, bond pads, solder balls, and/or other conductive media. The functioning of DUTs may be tested by invoking stimuli on various inputs and then measuring responses on outputs at the metallized contact surfaces.
Generally, a tester load board formed from a printed circuit board (PCB) or other media, provides interface between an ATE and DUTs. The tester load board conventionally includes one or more contactor assembly, sometimes referred to as “test socket(s)” into which DUT(s) is (are) inserted. During automated testing, a DUT, such as a BGA for example, is thrust into the socket by the handler and held into position for the duration of testing. While held in the socket, contact surfaces on the DUT, such as solder balls in the case of a BGA, make contact with the contactor pins. After insertion into the contactor, the DUT is electrically connected to the ATE through the tester load board, its sub assemblies, and other interfacing apparatus. FIG. 1 (prior art) will be familiar to those reasonably skilled in the arts. For the purposes illustrating a context in which the invention may be used, FIG. 1 (prior art) represents a simplified schematic example of a DUT 10 brought into contact with pogo pins 12 carried by a contactor body 14 and coupled by a tester load board 16 to an ATE 18. The ATE 18 is generally supplied with numerous stored instructions governing the actual testing procedures according to the requirements of the particular type of DUT.
This type of testing presents technical challenges in order to adequately verify the operation of the DUTs while avoiding false readings which result in the erroneous rejection of operable DUTs. One of the challenges encountered in this type of testing is ensuring adequate electrical contact between the contact pins associated with the contactor, and the contact surfaces of the DUT. Poor electrical contact, often due to the presence of contaminants, can result in erroneous test readings. These readings can be indicative of IC failure modes to include continuity, functional, parametric or others common to semiconductor testing. Such erroneous readings can lead to the false rejection of otherwise good DUTs resulting in yield loss. Some yield recovery may be possible through retesting. By either accepting the erroneous yield loss or by retesting to achieve recovery, production costs are elevated.
Typically, a test “lot” includes numerous devices tested serially or in parallel which are subjected to the same testing process. A device handler thrusts each DUT into a socket where it is held in position, tested, removed, and then either rejected or accepted based on the results obtained by the ATE. Over the course of lot testing, debris may accumulate and contaminate the contact pins. This debris may originate from the testing and handling process itself, or may include manufacturing residue from the fabrication and/or assembly process(es) or from other sources. In addition to the presence of contaminants, repeatedly forcing electrical current through the necessarily small contact pins can degrade the conductivity characteristics of their contact surfaces, reducing their capacity to make secure contact. As contaminants accumulate coupled with degradation of contact surfaces, contact resistance (CRES) rises, thereby reducing the reliability of the tests. This rise in CRES may impact yield and/or test time as yield recovery testing increases. Ultimately manufacturing cost will tend to escalate.
Attempts to address the problem of fouled testing apparatus known in the arts include manually cleaning the contactor and its contact pins. Such approaches typically include some combination of brushing, blowing, rinsing, and sweeping the contact pins and/or contactor bodies. A major drawback common to these prior art techniques is the requirement that the testing be interrupted so that the tester load board with contactor assembly can be removed from the test cell. After cleaning, the tester load board with the contactor assembly must be reinstalled on the test cell and the test environment reestablished so that testing may resume. In some cases, the contact pins themselves are removed from the contactor body, cleaned, and replaced as well. Due to these and other problems, it would be useful and advantageous to provide apparatus and methods for testing semiconductor devices using improved cleaning techniques that ensure adequate electrical contact between test equipment and DUTs while avoiding the detachment of the tester load board and/or its subcomponents from the test cell, thereby reducing interruptions of the testing process.